Rambus Inc., a premier chip and silicon IP provider making data faster and safer, today announced an industry-leading Power Management IC (PMIC) for LPDDR6 SOCAMM2. The new LPDDR6 SOCAMM2 PMIC targets low-power, high-performance Small Outline Compression Attached Memory Modules (SOCAMM2). Rambus developed the chip in technical cooperation with customers and ecosystem partners. It supports future-generation accelerated AI infrastructure. Moreover, the launch expands the Rambus family of LPDDR-based server module chips. It also extends the company’s leadership in advanced server memory products.
Why Tokens per Watt Matter for AI Workloads
AI training and inference workloads continue to scale. As a result, operators need higher throughput within a given power envelope. Industry players measure this metric in tokens per watt. It now stands as a critical consideration for AI infrastructure. Consequently, demand is rising for purpose-built memory solutions. These solutions must optimize power efficiency, form factor, and scalability.
SOCAMM2 answers that need. It brings the power and performance benefits of LPDDR technology to a compact, modular, and serviceable server-memory architecture. Designers built this architecture for demanding AI systems. Meanwhile, LPDDR6 SOCAMM2, now in development, represents the next important evolution in LPDDR-based server memory technology.
Rami Sethi, senior vice president and general manager of Memory Interface Chips at Rambus, shared his view on the launch.
“Inference and agentic AI are driving exciting new opportunities for memory innovation across the data center,” said Rami Sethi, senior vice president and general manager of Memory Interface Chips at Rambus. “Our new PMIC designed for LPDDR6 SOCAMM2 builds on our leadership in server-memory power management. Working closely with industry leaders in alignment with the broader AI ecosystem, we are helping enable the high-performance, power-efficient memory architectures that maximize tokens per watt for AI workloads.”
Similarly, Micron Technology welcomed the announcement.
“As AI systems place growing demands on memory capacity, bandwidth and power efficiency, LPDRAM is becoming an increasingly important technology for next-generation AI infrastructure,” said Praveen Vaidyanathan, vice president and general manager of Cloud Memory Products at Micron Technology. “Micron has helped pioneer low-power memory for the data center and continues to work closely with ecosystem partners to advance industry standards such as SOCAMM2. We welcome Rambus’ continued investment in LPDDR6 power management solutions, which help strengthen the broader low-power memory ecosystem.”
Building on Rambus Server Memory Power Management Leadership
Rambus provides complete memory interface chipsets for DDR- and LPDDR-based memory modules. The portfolio includes registering clock drivers (RCDs), PMICs, voltage regulators, SPD Hubs, and temperature sensors. Meanwhile, the company continues to advance its memory module chipset roadmaps for high-volume CPU-based servers. At the same time, it expands its portfolio to address emerging memory architectures for accelerated AI infrastructure.
Rambus already offers a complete LPDDR5X SOCAMM2 chipset. This chipset provides the power delivery, configuration, and telemetry functions that current-generation SOCAMM2 requires. Building on this strategy, the new LPDDR6 SOCAMM2 PMIC and the Rambus SPD Hub extend the LPDDR-based module roadmap. Together, they support the evolving requirements of the upcoming LPDDR6 SOCAMM2.
Engineers optimized the PMIC and SPD Hub for the dynamic workload conditions of future AI systems. Furthermore, both chips deliver efficient and precise module-level power management. This includes advanced power conversion, sequencing, telemetry, and fault protection. The PMIC steps down the system voltage supply efficiently. It then delivers the voltage levels that the LPDDR6 DRAM and all other active chips on the module need. Ultimately, these capabilities support the performance, reliability, and power efficiency that next-generation accelerated computing platforms demand.
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News Source: Businesswire.com
