Keysight Technologies just launched a new PCIe 7.0 Receiver (RX) Test application. This addition helps engineers tackle the massive challenge of validating performance at 128 GT/s. These speeds are critical for the next generation of compute, AI, and data center applications. The new solution provides end-to-end transmitter and receiver validation. It addresses a defining hurdle for the industry as the PCIe 7.0 standard moves toward adoption.
The setup combines high-performance hardware to handle increased complexity. It uses the M8050A BERT family along with the M8042A 120 GBaud pattern generator. The M8043A error analyzer is also included to provide accurate signal analysis for ASIC validation. To make things easier, Keysight added the N5991PB7A software. This tool automates the calibration of stressed signals. It significantly reduces the manual setup effort usually required for these tests.
Automated Calibration for PCIe 7.0 Receivers
Validating receivers at 128 GT/s often leads to serious signal integrity issues. Keysight’s new automated workflows help find these weaknesses early in the design phase. This prevents expensive, late-stage rework for hardware teams. The system operates in common clock mode to streamline the entire validation process. Engineers can now develop and deploy their advanced ASIC designs with much more confidence.
Dr. Joachim Peerlings, Vice President of Network and Data Center Solutions at Keysight, stated: “PCIe 7.0 receiver validation at 128 GT/s is one of the industry’s most significant signal integrity challenges. By extending our PCIe 7.0 physical‑layer measurement portfolio with advanced receiver characterization capabilities, we help customers reduce risk, accelerate development, and confidently validate next-generation ASIC designs.”
The company is currently demonstrating this solution at the PCI-SIG Developers Conference. This event is taking place in Santa Clara, California, from May 6-7, 2026. It marks the first time these tools have been shown to the public. Keysight continues to enable end-to-end physical-layer validation for the evolving PCIe ecosystem.
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News Source: Businesswire.com
